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cy8cled02 ez-color? hb led controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-13704 rev. *e revised december 15, 2010 features hb led controller ? configurable dimmers support up to 2 independent led channels ? 8-32 bits of resolution per channel ? dynamic reconfiguration enables led controller plus other features; battery charging, motor control visual embedded design ? led-based drivers ? binning compensation ? temperature feedback ? optical feedback ?dmx512 prism modulation technology ? reduces radiated emi ? reduces low frequency blinking powerful harvard architecture processor ? m8c processor speeds to 24 mhz ? 3.0 to 5.25v operating voltage ? operating voltages down to 1.0v using on-chip switch mode pump (smp) ? industrial temperature range: -40c to +85c flexible on-chip memory ? 4k flash program storage 50,000 erase/write cycles ? 256 bytes sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash advanced peripherals (psoc blocks) ? 4 digital psoc blocks provide: ? 8 to 32-bit timers, counters, and pwms ? full-duplex uart ? multiple spi masters or slaves ? connectable to all gpio pins ? 4 rail-to-rail analog psoc blocks provide: ? up to 14-bit adcs ? up to 9-bit dacs ? programmable gain amplifiers ? programmable filters and comparators ? complex peripherals by combining blocks programmable pin configurations ? 25 ma sink, 10 ma source on all gpio ? pull up, pull down, high z, strong, or open drain drive modes on all gpio ? up to 12 analog inputs on gpio ? four 30 ma analog outputs on gpio ? configurable interrupt on all gpio complete development tools ? free development software ? psoc designer? ? full featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128 kbytes trace memory logic block diagram digital system sram system bus interrupt controller sleep and watchdog clock sources (includes imo and ilo) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash i2c internal voltage ref. digital clocks por and lvd system resets system resources analog system analog ref. port 1 port 0 digital psoc block array analog psoc block array switch mode pump [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 2 of 44 contents features ...............................................................................1 logic block diagram ..........................................................1 contents ..............................................................................2 ez-color? functional overview .......................................3 target applications ........................................................3 the psoc core .............................................................3 the digital system ........................................................3 the analog system .......................................................4 additional system resources .......................................4 ez-color device characteristi cs ...................................5 getting started ....................................................................5 development kits ..........................................................5 training .........................................................................5 cypros consultants .......................................................5 technical support .........................................................5 application notes ..........................................................5 development tools ............................................................6 psoc designer software subsyst ems ............ ..............6 in-circuit emulator .........................................................6 document conventions .....................................................7 acronyms used .............................................................7 units of measure ...........................................................7 numeric naming ............................................................7 pin information ...................................................................8 pinouts ..........................................................................8 register reference .................. .........................................10 register conventions ..................................................10 register mapping tables ........ ............... .............. .......10 electrical specifications ..................................................13 absolute maximum ra tings .........................................14 operating temperature ...............................................14 dc electrical characteristics .......................................15 ac electrical characteristics .......................................22 packaging information .....................................................31 thermal impedances ..................................................34 solder reflow peak temperat ure ...............................34 development tool selection ..... .............. .............. ..........35 software tools ............................................................35 hardware tools ...........................................................35 evaluation tools ..........................................................35 device programmers ............. ......................................36 accessories (emulation and programming) ................36 ordering information ........................................................37 key device features ...................................................37 ordering code definitions ..... ......................................37 document history page .......... .........................................38 sales, solutions, and legal information ........................39 worldwide sales and design supp ort ............ .............39 products ......................................................................39 psoc solutions ...........................................................39 [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 3 of 44 ez-color? functional overview cypress's ez-color family of devices offers the ideal control solution for high brightness led applications requiring intel- ligent dimming control. ez-color devices combine the power and flexibility of psoc (programmable system-on-chip?); with cypress' prism (precise illumination signal modulation) drive technology providing lighting designers a fully customizable and integrated lighting solution platform. the ez-color family supports a range of independent led channels from 4 channels at 32 bits of resolution each, up to 16 channels at 8 bits of resolution each. this enables lighting designers the flexibility to choose the led array size and color quality. psoc designer software, with lighting specific drivers, can significantly cut development time and simplify implemen- tation of fixed color points thro ugh temperature, op tical, and led binning compensation. ez-color's virtually limitless analog and digital customization enables the simple integration of features in addition to intelligent lighting, such as battery charging, image stabilization, and motor control during the development process. these features, alo ng with cypress's best-in-class quality and design support, make ez-color the ideal choice for intelligent hb led control applications. target applications lcd backlight large signs general lighting architectural lighting camera/cell phone flash flashlights the psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and an imo (internal main oscillator) and an ilo (internal low speed oscil- lator). the cpu core, called the m8c, is a powerful, four mips, 8-bit harvard architecture microprocessor with speeds up to 24 mhz. system resources provide additional capability, such as digital clocks to increase the flexibility of the psoc; i2c functionality for implementing an i2c master, slave, or multi-master; an internal voltage reference that provides an absolute value of 1.3v to a number of psoc subsystems; a switch mode pump (smp) that generates normal operating voltages off a single battery cell; and various system resets supported by the m8c. the digital system is composed of an array of digital blocks, which can be configured into any number of digital peripherals. the digital blocks can be connected to the gpio through a series of global busses that can route any signal to any pin, freeing designers from the constraints of a fixed peripheral controller. the analog system consists of four analog blocks, supporting comparators, and analog-to-digital conversion up to 10 bits of precision. the digital system the digital system is composed of four digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to fo rm 8, 16, 24, and 32-bit periph- erals, which are called user modules. digital peripheral configu- rations include those listed below. prism (8 to 32 bit) pwms (8 to 32 bit) pwms with dead band (8 to 32 bit) counters (8 to 32 bit) timers (8 to 32 bit) uart 8 bit with selectable parity spi master and slave i2c slave, master, multi-master (1 available as a system resource) cyclical redundancy checker/generator (8 to 32 bit) irda (up to 4) generators (8 to 32 bit) connect the digital blocks to any gpio through a series of global busses that can route any signal to any pin. the busses also allow for signal multiplexing and for performing logic operations. this configurability frees your de signs from the constraints of a fixed peripheral controller. digital blocks are provided in ro ws of four, where the number of blocks varies by device family . this allows you the optimum choice of system resources fo r your application. family resources are shown in the table titled ez-color device charac- teristics. figure 1. digital system block diagram digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 1 port 0 [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 4 of 44 the analog system the analog system is composed of four configurab le blocks that enable creation of complex analog signal flows. analog periph- erals are very flexible and can be customized to support specific application requirements. some of the more common ez-color analog functions (most available as user modules) are listed below. analog-to-digital converters (single or dual, with 10-bit resolution) pin-to-pin comparators (1) single-ended comparators (up to 2) with absolute (1.3v) reference or 8-bit dac reference 1.3v reference (as a system resource) in most psoc based devices, analog blocks are provided in columns of three, which includes one ct (continuous time) and two sc (switched capacitor) blocks. this particular ez-color device provides limited functi onality type ?e? analog blocks. each column contains one ct block and one sc block. figure 2. analog system block diagram additional system resources system resources, some of wh ich have been previously listed, provide additional capability useful to complete systems. additional resources include: digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated us ing digital blocks as clock dividers. the i2c module provides 100 and 400 khz communication over two wires. slave, master, and multi-master modes are all supported. low voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced por (power on reset) circuit eliminates the need for a system supervisor. an internal 1.3 voltage reference provides an absolute reference for the analog system, including adcs and dacs. an integrated switch mode pump (smp) generates normal operating voltages from a single 1.2v battery cell, providing a low cost boost converter. acol1mux ace00 ace01 array array input configuration aci0[1:0] aci1[1:0] ase10 ase11 [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 5 of 44 ez-color device characteristics depending on your ez-color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6 , or 4 analog blocks. the following tabl e lists the resources available for specific ez-c olor device groups. th e device covered by thi s data sheet is shown in the highlighted row of the table getting started the quickest path to understandi ng the ez-color silicon is by reading this data sheet and usi ng the psoc designer integrated development environment (ide). this data sheet is an overview of the ez-color integrated ci rcuit and presents specific pin, register, and electrical specifications. for up-to-date ordering, packaging , and electrical specification information, reference the latest device data sheets on the web at http://www.cypress.com . development kits psoc development kits are available online from cypress at http://www.cypress.com and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free technical training (on demand, webinars, and workshops) is available online at http://www.cypress.com . the training covers a wide variety of topics an d skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to http://www.cypress.com and refer to cypros consultants. technical support for assistance with technical issues, search knowledge base articles and forums at http://www.cypress.com . if you cannot find an answer to your question, call technical support at 1-800-541-4736. application notes application notes are an excellent introduction to the wide variety of possible psoc designs and are available at http://www.cypress.com . table 1. ez-color device characteristics part number led channels digital i/o digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size capsense cy8cled02 2 16 1 4 8 0 2 4 256 bytes 4k no cy8cled04 4 56 1 4 48 2 2 6 1k 16k yes cy8cled08 8 44 2 8 12 4 4 12 256 bytes 16k no cy8cled16 16 44 4 16 12 4 4 12 2k 32k no [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 6 of 44 development tools psoc designer is a microsoft ? windows-based, integrated development environment for the programmable system-on-chip (psoc) devices. the psoc designer ide runs on windows xp or windows vista. this system provides design database management by project, an integrated debugger with in -circuit emulator, in-system programming support, and built -in support for third-party assemblers and c compilers. psoc designer also supports c language compilers developed specifically for the devices in the psoc family. psoc designer software subsystems system-level view a drag-and-drop visual embedded system design environment based on psoc express. in the system level view you create a model of your system inputs, ou tputs, and comm unication inter- faces. you define when and how an output device changes state based upon any or all other syst em devices. based upon the design, psoc designer automatically selects one or more psoc mixed-signal controllers that match your system requirements. psoc designer generates all embedded code, then compiles and links it into a programming file for a specific psoc device. chip-level view the chip-level view is a more traditional integrated development environment (ide). choose a bas e device to work with and then select different onboard analog and digital components called user modules that use the pso c blocks. examples of user modules are adcs, dacs, amplifie rs, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the device editor also supports easy development of multiple configurations and dynamic reconfiguration. dynamic configuration allows for changing configurations at run time. hybrid designs you can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. all views of the project share a common code editor, builder, and common deb ug, emulation, and programming tools. code generation tools psoc designer supports multiple third party c compilers and assemblers. the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. the choice is yours. assemblers. the assemblers allow a ssembly code to merge seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers. c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all the features of c tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger the psoc designer debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an inter nal view of the psoc device. debugger commands allow the designer to read and program and read and write data memory, read and write i/o registers, read and write cpu registers, set and clear breakpoints, and provide program run, halt, and st ep control. the debugger also allows the designer to create a trace buffer of registers and memory locations of interest. online help system the online help system displays on line, context-sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its ow n context-sensitive help. this system also provides tutorials an d links to faqs and an online support forum to aid the designer in getting started. in-circuit emulator a low cost, high functionality in-circuit emulator (ice) is available for development support. this hardware has the capability to progra m single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and operates with all psoc devices. emulation p ods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation. [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 7 of 44 pin information pinouts this section describes, lists, and illustrates the cy8cled02 ez-c olor device pins and pinout conf igurations. the cy8cled02 devi ce is available in a variety of packages which are listed and illus trated in the following tables. every port pin (labeled with a ?p?) is capable of digital i/o. however, vss, vdd, smp, and xres are not capable of digital i/o. 8-pin part pinout 16-pin part pinout table 2. 8-pin part pinout (soic) pin no. type pin name description figure 3. 8-pin ez-color device digital analog 1 i/o i p0[5] analog column mux input. 2 i/o i p0[3] analog column mux input. 3 i/o p1[1] i2c serial clock (scl), issp-sclk. 4 power vss ground connection. 5 i/o p1[0] i2c serial data (sda), issp-sdata. 6 i/o i p0[2] analog column mux input. 7 i/o i p0[4] analog column mux input. 8 power vdd supply voltage. legend : a = analog, i = input, and o = output. soic 1 2 3 4 8 7 6 5 vdd p0[4], a, i p0[2], a, i p1[0], i2c sda a, i, p0[5] a, i, p0[3] i2c scl, p1[1] vss table 3. 16-pin part pinout (soic) pin no. type name description figure 4. 16-pin ez-color device digital analog 1 i/o i p0[7] analog column mux input. 2 i/o i p0[5] analog column mux input. 3 i/o i p0[3] analog column mux input. 4 i/o i p0[1] analog column mux input. 5 power smp switch mode pump (smp) connection to required external components. 6 power vss ground connection. 7 i/o p1[1] i2c serial clo ck (scl), issp-sclk. 8 power vss ground connection. 9 i/o p1[0] i2c serial data (sda), issp-sdata. 10 i/o p1[2] 11 i/o p1[4] optional external clock input (extclk). 12 i/o i p0[0] analog column mux input. 13 i/o i p0[2] analog column mux input. 14 i/o i p0[4] analog column mux input. 15 i/o i p0[6] analog column mux input. 16 power vdd supply voltage. legend a = analog, i = input, and o = output. soic vdd p0[6], a, i p0[4], a, i p0[2], a, i p0[0], a, i p1[4], extclk p1[2] p1[0], i2c sda 16 15 14 13 12 11 1 2 3 4 5 6 7 8 a, i, p0[7] a, i, p0[5] a, i, p0[3] a, i, p0[1] smp vss i2c scl, p1[1] vss 10 9 [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 8 of 44 24-pin part pinout notes 1. these are the issp pins, which are not high z at por (power on reset). 2. the center pad on the qfn package should be connected to ground (vss) for best mechanical, thermal, and electrical performanc e. if not connected to ground, it should be electrically floated and not connected to any other signal. table 4. 24-pin part pinout (qfn) [2] pin no. type name description figure 5. 24-pin ez-color device digital analog 1 i/o i p0[1] analog column mux input. 2 power smp switch mode pump (smp) connection to required external components. 3 power vss ground connection. 4 i/o p1[7] i2c serial clock (scl). 5 i/o p1[5] i2c serial data (sda). 6 i/o p1[3] 7 i/o p1[1] i2c serial clock (scl), issp-sclk [1] . 8 nc no connection. 9 power vss ground connection. 10 i/o p1[0] i2c serial data (sda), issp-sdata [1] . 11 i/o p1[2] 12 i/o p1[4] optional exte rnal clock input (extclk). 13 i/o p1[6] 14 input xres active high external reset with internal pull down. 15 nc no connection. 16 i/o i p0[0] analog column mux input. 17 i/o i p0[2] analog column mux input. 18 i/o i p0[4] analog column mux input. 19 i/o i p0[6] analog column mux input. 20 power vdd supply voltage. 21 power vss ground connection. 22 i/o i p0[7] analog column mux input. 23 i/o i p0[5] analog column mux input. 24 i/o i p0[3] analog column mux input. legend a = analog, i = input, and o = output. qfn (top view ) a, i, p0[1] smp vss i2c scl, p1[7] i2c sda, p1[5] p1[3] 1 2 3 4 5 6 18 17 16 15 14 13 p0[4], a, i p0[2], a, i nc xres p1[6] 24 23 22 21 20 19 p0[3], a, i p0[5], a, i p0[7], a, i vss vdd p0[6], a, i 7 8 9 10 11 12 i2c scl, p1[1] nc vss i2c sda, p1[0] p1[2] extclk, p1[4] p0[0], a, i [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 9 of 44 register reference register conventions this section lists the registers of the cy8cled02 ez-color device. the register conventions specific to this section are listed in the following table. register mapping tables the device has a total register address space of 512 bytes. the register space is referred to as i/o space and is divided into two banks. the xoi bit in the flag register (cpu_f) determines which bank the user is currently in. when the xoi bit is set the user is in bank 1. note in the following register mapping tables, blank fields are reserved and should not be accessed. table 5. register conventions convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 10 of 44 table 6. register map bank 0: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 ase10cr0 80 rw c0 prt0ie 01 rw 41 81 c1 prt0gs 02 rw 42 82 c2 prt0dm2 03 rw 43 83 c3 prt1dr 04 rw 44 ase11cr0 84 rw c4 prt1ie 05 rw 45 85 c5 prt1gs 06 rw 46 86 c6 prt1dm2 07 rw 47 87 c7 08 48 88 c8 09 49 89 c9 0a 4a 8a ca 0b 4b 8b cb 0c 4c 8c cc 0d 4d 8d cd 0e 4e 8e ce 0f 4f 8f cf 10 50 90 d0 11 51 91 d1 12 52 92 d2 13 53 93 d3 14 54 94 d4 15 55 95 d5 16 56 96 i2c_cfg d6 rw 17 57 97 i2c_scr d7 # 18 58 98 i2c_dr d8 rw 19 59 99 i2c_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c dc 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f df dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w 61 a1 int_msk1 e1 rw dbb00dr2 22 rw pwm_cr 62 rw a2 int_vc e2 rc dbb00cr0 23 # 63 a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 e4 dbb01dr1 25 w 65 a5 e5 dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # adc0_cr 68 # a8 e8 dcb02dr1 29 w adc1_cr 69 # a9 e9 dcb02dr2 2a rw 6a aa ea dcb02cr0 2b # 6b ab eb dcb03dr0 2c # tmp_dr0 6c rw ac ec dcb03dr1 2d w tmp_dr1 6d rw ad ed dcb03dr2 2e rw tmp_dr2 6e rw ae ee dcb03cr0 2f # tmp_dr3 6f rw af ef 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 ace00cr1 72 rw rdi0is b2 rw f2 33 ace00cr2 73 rw rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 ace01cr1 76 rw rdi0ro1 b6 rw f6 37 ace01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and should no t be accessed. # access is bit specific. [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 11 of 44 table 7. register map bank 1: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 ase10cr0 80 rw c0 prt0dm1 01 rw 41 81 c1 prt0ic0 02 rw 42 82 c2 prt0ic1 03 rw 43 83 c3 prt1dm0 04 rw 44 ase11cr0 84 rw c4 prt1dm1 05 rw 45 85 c5 prt1ic0 06 rw 46 86 c6 prt1ic1 07 rw 47 87 c7 08 48 88 c8 09 49 89 c9 0a 4a 8a ca 0b 4b 8b cb 0c 4c 8c cc 0d 4d 8d cd 0e 4e 8e ce 0f 4f 8f cf 10 50 90 gdi_o_in d0 rw 11 51 91 gdi_e_in d1 rw 12 52 92 gdi_o_ou d2 rw 13 53 93 gdi_e_ou d3 rw 14 54 94 d4 15 55 95 d5 16 56 96 d6 17 57 97 d7 18 58 98 d8 19 59 99 d9 1a 5a 9a da 1b 5b 9b db 1c 5c 9c dc 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw cmp_go_en 64 rw a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 adc0_tr e5 rw dbb01ou 26 rw amd_cr1 66 rw a6 adc1_tr e6 rw 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 a8 imo_tr e8 w dcb02in 29 rw 69 a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b clk_cr3 6b rw ab eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw ac ec dcb03in 2d rw tmp_dr1 6d rw ad ed dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 ace00cr1 72 rw rdi0is b2 rw f2 33 ace00cr2 73 rw rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 ace01cr1 76 rw rdi0ro1 b6 rw f6 37 ace01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fls_pr1 fa rw 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and should no t be accessed. # access is bit specific. [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 12 of 44 electrical specifications this section presents the dc and ac electric al specifications of the cy8c led02 ez-color device. for the most up to date electri cal specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com. specifications are valid for -40c t a 85c and t j 100c, except where noted. refer to table 21 for the electrical specifications on the internal ma in oscillator (imo) using slimo mode. figure 6. voltage versus cpu frequency, and voltage versus imo frequency 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage 5.25 4.75 3.00 93 khz 12 mhz 24 mhz imo frequency vdd voltage 3.60 6 mhz slimo mode = 0 slimo mode=0 2.40 slimo mode=1 slimo mode=1 slimo mode=1 2.40 3 mhz v a l i d o p e r a t i n g r e g i o n slimo mode=1 slimo mode=0 [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 13 of 44 absolute maximum ratings operating temperature table 8. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 25 +100 c higher storage temperatures reduce data retention time. recommended storage temperature is +25c 25c. extended duration storage tempera- tures above 65c degrade reliability. t baketemp bake temperature ? 125 see package label c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied -40 ? +85 c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tri-state vss - 0.5 ? vdd + 0.5 v i mio maximum current into any port pin -25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch up current ? ? 200 ma table 9. operating temperature symbol description min typ max units notes t a ambient temperature -40 ? +85 c t j junction temperature -40 ? +100 c the temperature rise from ambient to junction is package specific. see thermal impedances on page 33 . the user must limit the power consumption to comply with this requirement. [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 14 of 44 dc electrical characteristics dc chip-level specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40c t a 85c, 3.0v to 3.6v and -40c t a 85c, or 2.4v to 3.0v and -40c t a 85c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25c and are for design guidance only. table 10. dc chip-level specifications symbol description min typ max units notes vdd supply voltage 2.40 ? 5.25 v see dc por and lvd specifications, table 18 on page 19. i dd supply current, imo = 24 mhz ? 3 4 ma conditions are vdd = 5.0v, 25c, cpu = 3 mhz, sysclk doubler disabled. vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.366 khz. i dd3 supply current, imo = 6 mhz ? 1.2 2 ma conditions are vdd = 3.3v, 25c, cpu = 3 mhz, clock doubler disabled. vc1 = 375 khz, vc2 = 23.4 khz, vc3 = 0.091 khz. i dd27 supply current, imo = 6 mhz ? 1.1 1.5 ma conditions are vdd = 2.55v, 25c, cpu = 3 mhz, clock doubler disabled. vc1 = 375 khz, vc2 = 23.4 khz, vc3 = 0.091 khz. i sb27 sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. mid temperature range. ? 2.6 4 a vdd = 2.55v, 0c to 40c. i sb sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. ? 2.8 5 a vdd = 3.3v, -40c t a 85c. v ref reference voltage (bandgap) 1.28 1.30 1.32 v trimmed for appropriate vdd. vdd = 3.0v to 5.25v. v ref27 reference voltage (bandgap) 1.16 1.30 1.330 v trimmed for appropriate vdd. vdd = 2.4v to 3.0v. agnd analog ground v ref - 0.003 v ref v ref + 0.003 v [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 15 of 44 dc general purpose i/o specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40c t a 85c, 3.0v to 3.6v and -40c t a 85c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25c and are for design guidance only. table 11. 5v and 3.3v dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k r pd pull down resistor 4 5.6 8 k v oh high output level vdd - 1.0 ? ? v ioh = 10 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 80 ma maximum combined ioh budget. v ol low output level ? ? 0.75 v iol = 25 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 150 ma maximum combined iol budget. i oh high level source current 10 ? ? ma voh = vdd-1.0v. see the limitations of the total current in the note for voh. i ol low level sink current 25 ? ? ma vol = 0.75v. see the limit ations of the total current in the note for vol. v il input low level ? ? 0.8 v vdd = 3.0 to 5.25. v ih input high level 2.1 ? ? v vdd = 3.0 to 5.25. v h input hysteresis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25c. [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 16 of 44 the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 2.4v to 3.0v an d -40c t a 85c. typical parameters apply to 2.7v at 25c and are for design guidance only. dc amplifier specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75v to 5.25v and -40c t a 85c, 3.0v to 3.6v and -40c t a 85c, or 2.4v to 3.0v and -40c t a 85c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25c and are for design guidance only. table 12. 2.7v dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k r pd pull down resistor 4 5.6 8 k v oh high output level vdd - 0.4 ? ? v ioh = 2. 5 ma (6.25 typical), vdd = 2.4 to 3.0v (16 ma maximum, 50 ma typical combined ioh budget). v ol low output level ? ? 0.75 v iol = 10 ma, vdd = 2.4 to 3.0v (90 ma maximum combined iol budget). i oh high level source current 2.5 ? ? ma voh = vdd-0.4v. see the lim itations of the total current in the note for voh. i ol low level sink current 10 ? ? ma vol = 0.75v. see the limitations of the total current in the note for vol. v il input low level ? ? 0.75 v vdd = 2.4 to 3.0. v ih input high level 2.0 ? ? v vdd = 2.4 to 3.0. v h input hysteresis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25c. table 13. 5v dc amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25c. v cmoa common mode voltage range 0.0 ? vdd - 1 v g oloa open loop gain 80 ? ? db i soa amplifier supply current ? 10 30 a [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 17 of 44 dc low power comparator specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40c t a 85c, 3.0v to 3.6v and -40c t a 85c, or 2.4v to 3.0v and -40c t a 85c, respectively. typical parameters apply to 5v at 25c and are for design guidance only. table 14. 3.3v dc amplifier specifications symbol description min typ max units notes v osoa input offset voltage (abs olute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25c. v cmoa common mode voltage range 0 ? vdd - 1 v g oloa open loop gain 80 ? ? db i soa amplifier supply current ? 10 30 a table 15. 2.7v dc amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25c. v cmoa common mode voltage range 0 ? vdd - 1 v g oloa open loop gain 80 ? ? db i soa amplifier supply current ? 10 30 a table 16. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? vdd - 1 v i slpc lpc supply current ? 10 40 a v oslpc lpc voltage offset ? 2.5 30 mv [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 18 of 44 dc switch mode pump specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40c t a 85c, 3.0v to 3.6v and -40c t a 85c, or 2.4v to 3.0v and -40c t a 85c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25c and are for design guidance only. table 17. dc switch mode pump (smp) specifications symbol description min typ max units notes v pump5v 5v output voltage from pump 4.75 5.0 5.25 v configurat ion of footnote. [3] average, neglecting ripple. smp trip voltage is set to 5.0v. v pump3v 3.3v output voltage from pump 3.00 3.25 3.60 v configuration of footnote. [3] average, neglecting ripple. smp trip voltage is set to 3.25v. v pump2v 2.6v output voltage from pump 2.45 2.55 2.80 v configuration of footnote. [3] average, neglecting ripple. smp trip voltage is set to 2.55v. i pump available output current v bat = 1.8v, v pump = 5.0v v bat = 1.5v, v pump = 3.25v v bat = 1.3v, v pump = 2.55v 5 8 8 ? ? ? ? ? ? ma ma ma configuration of footnote. [3] smp trip voltage is set to 5.0v. smp trip voltage is set to 3.25v. smp trip voltage is set to 2.55v. v bat5v input voltage range from battery 1 .8 ? 5.0 v configuration of footnote. [3] smp trip voltage is set to 5.0v. v bat3v input voltage range from battery 1 .0 ? 3.3 v configuration of footnote. [3] smp trip voltage is set to 3.25v. v bat2v input voltage range from battery 1 .0 ? 2.8 v configuration of footnote. [3] smp trip voltage is set to 2.55v. v batstart minimum input voltage from battery to start pump 1.2 ? ? v configuration of footnote. [3] 0c t a 100. 1.25v at t a = -40c. v pump_line line regulation (over vi range) ? 5 ? %v o configuration of footnote. [3] v o is the ?vdd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 18 on page 19 . v pump_load load regulation ? 5 ? %v o configuration of footnote. [3] v o is the ?vdd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 18 on page 19 . v pump_ripple output voltage ripple (depends on cap/load) ? 100 ? mvpp configuration of footnote. [3] load is 5 ma. e 3 efficiency 35 50 ? % confi guration of footnote. [3] load is 5 ma. smp trip voltage is set to 3.25v. e 2 efficiency 35 80 ? % for i load = 1ma, v pump = 2.55v, v bat = 1.3v, 10 h inductor, 1 f capacitor, and schottky diode. f pump switching frequency ? 1.3 ? mhz dc pump switching duty cycle ? 50 ? % note 3. l 1 = 2 mh inductor, c 1 = 10 mf capacitor, d 1 = schottky diode. see figure 7 on page 19. [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 19 of 44 figure 7. basic switch mode pump circuit dc por and lvd specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40c t a 85c, 3.0v to 3.6v and -40c t a 85c, or 2.4v to 3.0v and -40c t a 85c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25c and are for design guidance only. battery c1 d1 + ez-color vdd vss smp v bat v pump l 1 table 18. dc por and lvd specifications symbol description min typ max units notes v ppor0 v ppor1 v ppor2 vdd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.36 2.82 4.55 2.40 2.95 4.70 v v v vdd must be greater than or equal to 2.5v during startup, reset from the xres pin, or reset from watchdog. v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 2.92 3.02 3.13 4.48 4.64 4.73 4.81 2.51 [4] 2.99 [5] 3.09 3.20 4.55 4.75 4.83 4.95 v v v v v v v v v pump0 v pump1 v pump2 v pump3 v pump4 v pump5 v pump6 v pump7 vdd value for pump trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.45 2.96 3.03 3.18 4.54 4.62 4.71 4.89 2.55 3.02 3.10 3.25 4.64 4.73 4.82 5.00 2.62 [6] 3.09 3.16 3.32 [7] 4.74 4.83 4.92 5.12 v v v v v v v v notes 4. always greater than 50 mv above ppor (porlev = 00) for falling supply. 5. always greater than 50 mv above ppor (porlev = 10) for falling supply. 6. always greater than 50 mv above v lvd0 . 7. always greater than 50 mv above v lvd3 . [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 20 of 44 dc programming specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40c t a 85c, 3.0v to 3.6v and -40c t a 85c, or 2.4v to 3.0v and -40c t a 85c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25c and are for design guidance only. dc i 2 c specifications ta b l e 2 0 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, 3.0 v to 3.6 v and ?40 c t a 85 c, or 2.4 v to 3.0 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 19. dc programming specifications symbol description min typ max units notes v ddp v dd for programming and erase 4.5 5.0 5.5 v this specification applies to the functional require- ments of external programmer tools v ddlv low v dd for verify 3.0 3.1 3.2 v this specification applies to the functional require- ments of external programmer tools v ddhv high v dd for verify 5.1 5.2 5.3 v this specification applies to the functional require- ments of external programmer tools v ddiwrite supply voltage for flash write operations 3.0 ? 5.25 v this specification applies to this device when it is executing internal flash writes i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull down resistor. v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd - 1.0 ? vdd v flash enpb flash endurance (per block) 50,000 [8] ? ? ? erase/write cycles per block. flash ent flash endurance (total) [9] 1,800,000 0 ? 0 ? 0 ? 0 erase/write cycles. 0 flash dr flash data retention 10 ? ? years table 20. dc i 2 c specifications [10] symbol description min typ max units notes v ili2c input low level ? ? 0.3 v dd v 3.0 v v dd 3.6 v ??0.25 v dd v4.75 v v dd 5.25 v v ihi2c input high level 0.7 v dd ? ? v 3.0 v v dd 5.25 v notes 8. the 50,000 cycle flash endurance per block will only be guarantee d if the flash is operating within one voltage range. voltag e ranges are 2.4v to 3.0v, 3.0v to 3.6v, and 4.75v to 5.25v. 9. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles eac h (to limit the total number of cycles to 36x5 0,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperatur e sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. 10. all gpio meet the dc gpio v il and v ih specifications mentioned in section dc general purpose i/o specifications on page 15 . the i 2 c gpio pins also meet [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 21 of 44 ac electrical characteristics ac chip-level specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40c t a 85c, 3.0v to 3.6v and -40c t a 85c, or 2.4v to 3.0v and -40c t a 85c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25c and are for design guidance only. table 21. 5-v and 3.3-v ac chip-level specifications symbol description min typ max units notes f imo24 imo frequency for 24 mhz 23.4 24 24.6 [11,12] mhz trimmed for 5 v or 3.3 v operation using factory trim values. refer to figure 6 on page 12. slimo mode = 0. f imo6 imo frequency for 6 mhz 5.5 6 6.5 [11,12] mhz trimmed for 3.3 v operation using factory trim values. see figure 6 on page 12. slimo mode = 1. f cpu1 cpu frequency (5 v nominal) 0.0937 24 24.6 [11] mhz 12 mhz only for slimo mode = 0. f cpu2 cpu frequency (3.3 v nominal) 0.0937 12 12.3 [12] mhz slimo mode = 0. f blk5 digital psoc block frequency 0 (5 v nominal) 0 48 49.2 [11,13] mhz refer to the section ac digital block specifications on page 25 . f blk33 digital psoc block frequency (3.3 v nominal) 0 24 24.6 [13] mhz f 32k1 ilo frequency 15 32 64 khz f 32k_u ilo untrimmed frequency 5 ? 100 khz after a reset and before the m8c starts to run, the ilo is not trimmed. see the system resets section of the psoc technical reference manual for details on this timing. t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % dc ilo ilo duty cycle 20 50 80 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.8 48.0 49.2 [11,12] mhz trimmed. using factory trim values. f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz sr power_up power supply slew rate ? ? 250 v/ms v dd slew rate during power-up. t powerup time from end of por to cpu executing code ? 16 100 ms power-up from 0 v. see the system resets section of the psoc technical reference manual . t jit_imo 24-mhz imo cycle-to- cycle jitter (rms) [14] ? 200 700 ps 24-mhz imo long term n cycle-to-cycle jitter (rms) [14] ? 300 900 ps n = 32 24-mhz imo period jitter (rms) [14] ? 100 400 ps notes 11. 4.75 v < v dd < 5.25 v. 12. 3.0 v < v dd < 3.6 v. refer to the application note, adjusting psoc microcontroller trims for dual voltage-range operation ? an2012 for more information on trimming for operation at 3.3 v. 13. see the individual user module datasheets for information on maximum frequencies for user modules. 14. refer to the application note, understanding datasheet jitter specificati ons for cypress timing products ? an5054 for more information on jitter specifications. [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 22 of 44 table 22. 2.7-v ac chip-level specifications symbol description min typ max units notes f imo12 imo frequency for 12 mhz 11.5 12 0 12.7 [15,16] mhz trimmed for 2.7 v operation using factory trim values. see figure 6 on page 12. slimo mode = 1. f imo6 imo frequency for 6 mhz 5.5 6 6.5 [15,16] mhz trimmed for 2.7 v operation using factory trim values. see figure 6 on page 12. slimo mode = 1. f cpu1 cpu frequency (2.7 v nominal) 0.093 3 3.15 [15] mhz 24 mhz only for slimo mode = 0. f blk27 digital psoc block frequency (2.7 v nominal) 0 12 12.5 [15,16] mhz refer to the section ac digital block specifications on page 25 . f 32k1 ilo frequency 8 32 96 khz f 32k_u ilo untrimmed frequency 5 ? 100 khz after a reset and before the m8c starts to run, the ilo is not trimmed. see the system resets section of the psoc technical reference manual for details on this timing. t xrst external reset pulse width 10 ? ? s dc ilo ilo duty cycle 20 50 80 % f max maximum frequency of signal on row input or row output ? ? 12.3 mhz sr power_up power supply slew rate ? ? 250 v/ms v dd slew rate during power-up. t powerup time from end of por to cpu executing code ? 16 100 ms power-up from 0 v. see the system resets section of the psoc technical reference manual . t jit_imo 12-mhz imo cycle-to-cycle jitter (rms) [17] ? 400 1000 ps 12-mhz imo long term n cycle-to-cycle jitter (rms) [17] ? 600 1300 ps n = 32 12-mhz imo period jitter (rms) [17] ? 100 500 ps notes 15. 2.4 v < v dd < 3.0 v. 16. refer to the application note adjusting psoc microcontroller trims for dual voltage-range operation ? an2012 for more information on maximum frequency for user modules. 17. refer to the application note, understanding datasheet jitter specifications for cypress timing products ? an5054 for more information on jitter specifications. [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 23 of 44 ac gpio specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40c t a 85c, 3.0v to 3.6v and -40c t a 85c, or 2.4v to 3.0v and -40c t a 85c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25c and are for design guidance only. figure 8. gpio timing diagram ac amplifier specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75v to 5.25v and -40c t a 85c, 3.0v to 3.6v and -40c t a 85c, or 2.4v to 3.0v and -40c t a 85c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25c and are for design guidance only.settling times, slew rates, and gain bandwidth are based on the analog continuous time psoc block. table 23. 5v and 3.3v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns vdd = 3 to 5.25v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns vdd = 3 to 5.25v, 10% - 90% table 24. 2.7v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 3 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 6 ? 50 ns vdd = 2.4 to 3.0v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 6 ? 50 ns vdd = 2.4 to 3.0v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 18 40 120 ns vdd = 2.4 to 3.0v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 18 40 120 ns vdd = 2.4 to 3.0v, 10% - 90% tfallf tfalls trisef trises 90% 10% gpio pin table 25. 5v and 3.3v ac amplifier specifications symbol description min typ max units notes t comp1 comparator mode response time, 50 mvpp signal centered on reference - - 100 ns t comp2 comparator mode respon se time, 2.5v input, 0.5v overdrive - - 300 ns [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 24 of 44 ac low power comparator specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40c t a 85c, 3.0v to 3.6v and -40c t a 85c, or 2.4v to 3.0v and -40c t a 85c, respectively. typical parameters apply to 5v at 25c and are for design guidance only. table 26. 2.7v ac amplifier specifications symbol description min typ max units notes t comp1 comparator mode response time, 50 mvpp signal centered on ref - - 600 ns t comp2 comparator mode respon se time, 1.5v input, 0.5v overdrive - - 300 ns table 27. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 s 50 mv overdrive comparator reference set within v reflpc . [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 25 of 44 ac digital block specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40c t a 85c, 3.0v to 3.6v and -40c t a 85c, or 2.4v to 3.0v and -40c t a 85c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25c and are for design guidance only. table 28. 5-v and 3.3-v ac digital block specifications function description min typ max unit notes all functions block input clock frequency v dd 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz timer input clock frequency no capture, v dd 4.75 v ? ? 49.2 mhz no capture, v dd < 4.75 v ? ? 24.6 mhz with capture ? ? 24.6 mhz capture pulse width 50 [18] ??ns counter input clock frequency no enable input, v dd 4.75 v ? ? 49.2 mhz no enable input, v dd < 4.75 v ? ? 24.6 mhz with enable input ? ? 24.6 mhz enable input pulse width 50 [18] ??ns dead band kill pulse width asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [18] ??ns disable mode 50 [18] ??ns input clock frequency v dd 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz crcprs (prs mode) input clock frequency v dd 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz crcprs (crc mode) input clock frequency ? ? 24.6 mhz spim input clock frequency ? ? 8.2 mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2. spis input clock (sclk) frequency ? ? 4.1 mhz the i nput clock is the spi sclk in spis mode. width of ss_negated between transmissions 50 [18] ??ns transmitter input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd 4.75 v, 2 stop bits ? ? 49.2 mhz v dd 4.75 v, 1 stop bit ? ? 24.6 mhz v dd < 4.75 v ? ? 24.6 mhz receiver input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd 4.75 v, 2 stop bits ? ? 49.2 mhz v dd 4.75 v, 1 stop bit ? ? 24.6 mhz v dd < 4.75 v ? ? 24.6 mhz note 18. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 26 of 44 ac external clock specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75v to 5.25v and -40c t a 85c, or 3.0v to 3.6v and -40c t a 85c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25c and are for design guidance only. table 29. 2.7-v ac digital block specifications function description min typ max units notes all functions block input clock frequency 12.7 mhz 2.4v < vdd < 3.0v. timer capture pulse width 100 [19] ? ? ns input clock frequency, with or without capture ? ? 12.7 mhz counter enable input pulse width 100 ? ? ns input clock frequency, no enable input ? ? 12.7 mhz input clock frequency, enable input ? ? 12.7 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 100 ? ? ns disable mode 100 ? ? ns input clock frequency ? ? 12.7 mhz crcprs (prs mode) input clock frequency ? ? 12.7 mhz crcprs (crc mode) input clock frequency ? ? 12.7 mhz spim input clock frequency ? ? 6.35 mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2. spis input clock (sclk) frequency ? ? 4.1 mhz width of ss_ negated between transmissions 100 ? ? ns transmitter input clock frequency ? ? 12.7 mhz the baud rate is equal to the input clock frequency divided by 8. receiver input clock frequency ? ? 12.7 mhz the baud rate is equal to the input clock frequency divided by 8. table 30. 5v ac external clock specificationsc symbol description min typ max units notes f oscext frequency 0.093 ?24.6mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ? s note 19. 100 ns minimum input pulse width is based on the input synchronizers running at 12 mhz (84 ns nominal period). [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 27 of 44 table 31. 3.3v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ? 12.3 mhz maximum cpu frequency is 12 mhz at 3.3v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 24.6 mhz if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider will ensure that the fift y percent duty cycle requirement is met. ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power up imo to switch 150 ? ? s table 32. 2.7v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ?6.06 0 mhz maximum cpu frequency is 3 mhz at 2.7v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 12.12 mhz if the frequency of the external clock is greater than 3 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider will ensure that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 83.4 ? 5300 ns ? low period with cpu clock divide by 1 83.4 ? ?ns ? power up imo to switch 150 ? ? s [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 28 of 44 ac programming specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40c t a 85c, or 3.0v to 3.6v and -40c t a 85c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25c and are for design guidance only. ac i 2 c specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40c t a 85c, 3.0v to 3.6v and -40c t a 85c, or 2.4v to 3.0v and -40c t a 85c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25c and are for design guidance only. table 33. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 10 ? ms t write flash block write time ? 80 ? ms t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 vdd 3.6 t dsclk2 data out delay from falling edge of sclk ? ? 70 ns 2.4 vdd 3.0 t erasea ll flash erase time (bulk) ? 20 ? ms erase all blocks and protection fields at once. t progra m_hot flash block erase + flash block write time ? ? 180 [20] ms 0c t j 100c t progra m_cold flash block erase + flash block write time ? ? 360 [20] ms -40c t j 0c table 34. ac characteristics of the i2c sda and scl pins for vcc . 3.0v symbol description standard-mode fast-mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c set-up time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data set-up time 0 250 0 ? 0 100 [21] ? 0 ns 0 t sustoi2c set-up time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ? 0 50 ns note 20. for the full industrial range, the user must employ a temper ature sensor user module (flashtemp) and feed the result to the temperature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 29 of 44 figure 9. definition for timing for fast-/standard-mode on the i 2 c bus table 35. 2.7v ac ch aracteristics of the i2c sda and scl pins (fast-mode not supported) symbol description standard-mode fast-mode units notes min max min max f scli2c scl clock frequency 0 100 ? ? khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ? ? ? s t lowi2c low period of the scl clock 4.7 ? ? ? s t highi2c high period of the scl clock 4.0 ? ? ? s t sustai2c set-up time for a repeated start condition 4.7 ? ? ? s t hddati2c data hold time 0 ? ? ? s t sudati2c data set-up time 250 ? ? ?ns t sustoi2c set-up time for stop condition 4.0 ? ? ? s t bufi2c bus free time between a stop and start condition 4.7 ?? ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ???ns note 21. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the sc l signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is released. 2c_sda 2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 30 of 44 packaging information this section illustrates the packaging spec ifications for the cy8cled02 ez-color dev ice, along with the thermal impedances for each package and minimum solder reflow peak temperature. important note emulation tools may require a larger ar ea on the target pcb than the chip's footprint. for a detailed description of the emulation tools' dimensions, refe r to the emulator pod drawings at http://www.cypress.com . figure 10. 8-pin (150-mil) soic 51-85066 *d [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 31 of 44 figure 11. 16-pin (150-mil) soic 51-85068 *b 51-85068 *c [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 32 of 44 figure 12. 24-pin (4x4) qfn important note for information on the preferred dimensions for mounting qfn pa ckages, see the following applicat ion note at "application notes for surface mount assembly of amkor's mi croleadframe (mlf) packages" available at h ttp://www.amkor.com. pinned vias for thermal conduction are not required for the low-power device. 51-85203 *b [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 33 of 44 thermal impedances solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. table 36. thermal impedances per package package typical ja [22] 8 soic 186c/w 16 soic 125c/w 24 qfn [23] 40c/w table 37. solder reflow peak temperature package maximum peak temperature time at maximum temperature 8 soic 260 c 20 s 16 soic 260 c 20 s 24 qfn 260 c 20 s notes 22. t j = t a + power x ja 23. to achieve the thermal impedance specified for the qfn package, refer to "application notes for surface mount assembly of am kor's microleadframe (mlf) packages" available at http://www.amkor.com . [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 34 of 44 development tool selection this section presents the development tools available for all current psoc based devices including the cy8cled02 ez-color family. software tools psoc designer at the core of the psoc development software suite is psoc designer, used to generate psoc firmware applications. psoc designer is available free of charge at http://www.cypress.com and includes a free c compiler. psoc programmer flexible enough to be used on the bench in development, yet suitable for factory progra mming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer. psoc programmer software is compatible with both psoc ice- cube in-circuit emulator and psoc miniprog. psoc programmer is available free ofcharge at http://www.cypress.com . hardware tools in-circuit emulator a low cost, high functionality ice (in-circuit emulator) is available for development support. this hardware has the capability to program single devices. the emulator consists of a base unit that connects to the pc by way of the usb port. the base unit is universal and will operate with all psoc based devices. emulation pods for each device family are available separately. the emulation pod takes the place of the device on the target board and performs full speed (24 mhz) operation. i2c to usb bridge the i2c to usb bridge is a quick and easy link from any design or application?s i2c bus to a pc via usb for design testing, debugging and communication. evaluation tools all evaluation tools can be purchased from the cypress online store. cy3261a-rgb ez-color rgb kit the cy3261a-rgb board is a preprogrammed hb led color mix board with seven pre-set colors using the cy8cled16 ez-color hb led controller. the board is accompanied by a cd containing the color selector software application, psoc designer, psoc programmer, and a suite of documents, schematics, and firmware examples. the color selector software application can be installed on a host pc and is used to control the ez-color hb led controller using the included usb cable. the application enables you to select colors via a cie 1931 chart or by entering coordinates. the kit includes: training board (cy8cled16) one mini-a to mini-b usb cable psoc designer cd-rom design files and application installation cd-rom to program and tune this kit via psoc designer you must use a mini programmer unit (cy3217 kit) and a cy3240-i2cusb kit. cy3263-colorlock evaluation kit the cy3263-colorlock evaluation board demonstrates the ability of the ez-color device to use real-time optical feedback to control three primary, high brig htness leds and create accurate, mixed-color output. the kit includes: cy3263-colorlock evaluation board tools cd, which includes: ? psoc programmer ? .net framework 2.0 (for windows 2000 and windows xp) ? psoc designer ? colorlock express pack ? cy3263-colorlock ez-color kit cd ? colorlock monitor application ? kit documents (quick start, kit guide, release note, appli- cation note, data sheets, schematics, and layouts) ? firmware retractable usb cable (a to mini-b) psoc miniprog programmer power supply adapter cy3265-rgb ez-color evaluation kit the cy3265-rgb evaluation board demonstrates the ability of the ez-color device to use real-time temperature feedback to control three primary, high brig htness leds and create accurate, mixed-color output. there are three variations of the kit available, depending on the led manufactur er of the leds on the board: cy3265c-rgb (cree leds), cy3 265n-rgb (nichia leds), or cy3265o-rgb (osram leds). the kit includes: cy3265c-rgb evaluation board tools cd, which includes: ? psoc programmer ? psoc designer ? .net framework 2.0 (windows xp 32 bit) kit documents (quick start, kit guide, release note, appli- cation note, data sheets, schematics, and layouts) firmware blue pca enclosure/case 12v 1a power supply retractable usb cable (a to mini-b) psoc miniprog programmer quick start guide [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 35 of 44 cy3210-miniprog1 the cy3210-miniprog1 kit allows a user to program psoc based devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, and plenty of bread- boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable device programmers all device programmers are sold at the cypress online store. cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base 3 programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production-programming environment. note cy3207issp needs spec ial software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240v power supply, euro-plug adapter usb 2.0 cable accessories (emula tion and programming) table 38. emulation and programming accessories part # pin package flex-pod kit [24] foot kit [25] adapter [26] CY8CLED02-8SXI 8 soic cy3250-led02 cy32 50-8soic-fk adapters can be found at http://www.emulation.com . cy8cled02-16sxi 16 soic cy3250-led02 cy3250-16soic-fk cy8cled02-24lfxi 24 qfn cy3250-led02qfn cy3250-24qfn-fk notes 24. flex-pod kit includes a practice flex-pod and a practice pcb, in addition to two flex-pods. 25. foot kit includes surface mount feet that can be soldered to the target pcb. 26. programming adapter converts non-dip package to dip footprin t. specific details and ordering information for each of the ada pters can be found at http://www.emulation.com. [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 36 of 44 ordering information key device features the following table lists the cy8cled02 ez-color de vices? key package feat ures and ordering codes. ordering code definitions table 39. device key features and ordering information package ordering code flash (bytes) ram (bytes) switch mode pump temperature range digital blocks analog blocks digital i/o pins analog inputs analog outputs xres pin 8 pin (150-mil) soic CY8CLED02-8SXI 4 k 256 no ?40 c to +85 c 4 4 6 4 0 no 8 pin (150-mil) soic (tape and reel) CY8CLED02-8SXIt 4 k 256 no ?40 c to +85 c 4 4 6 4 0 no 16 pin (150-mil) soic cy8cled02-16sxi 4 k 256 yes ?40 c to +85 c 4 4 12 8 0 no 16 pin (150-mil) soic (tape and reel) cy8cled02-16sxit 4 k 256 yes ?40 c to +85 c 4 4 12 8 0 no 24 pin (4x4) qfn cy8cled02-24lfxi 4 k 256 yes ?40 c to +85 c 4 4 16 8 0 yes 24 pin (4x4) qfn (tape and reel) cy8cled02-24lfxit 4 k 256 yes ?40 c to +85 c 4 4 16 8 0 yes cy 8 c led xx - xx xxxx package type: thermal rating: c = commercial sx = soic pb-free i = industrial lfx = qfn pb-free e = extended pin count part number led family code technology code: c = cmos marketing code: 8 = cypress psoc company id: cy = cypress [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 37 of 44 acronyms acronyms used ta b l e 4 0 lists the acronyms that are used in this document. reference documents design aids ? reading and writing psoc ? flash ? an2015 (001-40459) adjusting psoc ? trims for 3.3 v and 2.7 v operation ? an2012 (001-17397) understanding datasheet jitter specifications for cypress timing products ? an5054 (001-14503) application notes for surface mount assembly of amkor's microleadframe (mlf) packages ? available at http://www.amkor.com . table 40. acronyms used in this datasheet acronym description acronym description ac alternating current lpc low power comparator adc analog-to-digital converter mips million instructions per second api application programming interface pcb printed circuit board cmos complementary metal oxide semicon ductor pdip plastic dual-in-line package cpu central processing unit por power on reset crc cyclic redundancy check ppo r precision power on reset ct continuous time prs pseudo-random sequence dac digital-to-analog converter psoc? programmable system-on-chip dc direct current pwm pulse width modulator eeprom electrically erasable programmable read-only memory qfn quad flat no leads gpio general purpose i/o sc switched capacitor ice in-circuit emulator slimo slow imo ide integrated development environment smp switch mode pump ilo internal low speed oscillator soic small-outline integrated circuit imo internal main oscillator spi tm serial peripheral interface i/o input/output sram static random access memory irda infrared data association srom supervisory read only memory issp in-system serial programming uart univers al asynchronous reciever / transmitter lcd liquid crystal display usb universal serial bus lvd low voltage detect wdt watchdog timer led light-emitting diode xres external reset [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 38 of 44 document conventions units of measure ta b l e 4 1 lists the unit sof measures. numeric conventions hexadecimal numbers are represented with all letters in uppercase wi th an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimals. table 41. units of measure symbol unit of measure symbol unit of measure db decibels h microhenry c degree celsius s microsecond f microfarad ms millisecond pf picofarad ns nanosecond khz kilohertz ps picosecond mhz megahertz v microvolts k kilohm mv millivolts a microampere mvpp millivolts peak-to-peak ma milliampere v volts na nanoampere w watt pa pikoampere mm millimeter mh millihenry % percent glossary active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opamp circuits. these are sc (switched capacitor) and ct (continuous time) blocks. these blocks can be interconnected to provide adcs, dacs, mu lti-pole filters, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. application programming interface (api) a series of software routines that comprise an interface between a computer application and lower level services and functions (for exampl e, user modules and libraries). apis serve as building blocks for programmers that create softwa re applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the positive temperature coefficient of vt with the negative temperat ure coefficient of vbe, to produce a ze ro temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specific ally as, for example, full width at half maximum. [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 39 of 44 bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perfo rm one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for io operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and carrying similar data. typically represented using vector notation; fo r example, address[7:0]. 3. one or more conductors that serve as a co mmon connection for a group of related devices. clock the device that generates a periodic signal with a fixed frequen cy and duty cycle. a clock is sometimes used to synchroni ze different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler a program that translates a high leve l language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in whic h the frequency is controlled by a piezoelectric crystal. typically a piezoelectric crystal is less sensitive to ambient te mperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data co mmunications, typically performed using a linear feedback shift register. similar calculations may be used for a variety of other purposes such as data compression. data bus a bi-directional set of signals used by a comp uter to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allo ws you to analyze the operation of the system under development. a debugger usually allows th e developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic blocks that can act as a counter, timer, se rial receiver, serial transmitter, crc generator, pseudo-random number generator, or spi. glossary (continued) [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 40 of 44 digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog- to-digital (adc) converter pe rforms the reverse operation. duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emul ation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc device. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of eproms, pl us in-system erasability. non-volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be pr otected. a flash block holds 64 bytes. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, vo ltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to connect low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control el ectronics. i2c uses only two bi-d irectional pins, clock and data, both running at +5v and pulle d high with resistors. the bus operates at 100 kbits/second in standard mode an d 400 kbits/second in fast mode. ice the in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces da ta into or extracts data from a system. interrupt a suspension of a process, such as the ex ecution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code execution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exis t with its own priority and individual isr code block. each isr code block ends with the reti in struction, returning t he device to the point in the program where it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a ty pical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low-voltage detect (lvd) a circuit that senses v dd and provides an interrupt to the system when v dd falls lower than a selected threshold. m8c an 8-bit harvard-architecture microprocessor. the microprocessor coordinates all activity inside a psoc by interfacing to the fl ash, sram, and register space. glossary (continued) [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 41 of 44 master device a device that controls the timing for da ta exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external in terface. the controlled device is called the slave device . microcontroller an integrated circuit chip that is desi gned primarily for control systems and products. in addition to a cpu, a microcontroller typically includes memory, timing circuits, and io circuitry. the reason for this is to permit the realization of a co ntroller with a minimal quantity of chips, thus achieving maximal possible miniaturization. this in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or mo re characteristics of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation bet ween the logical inputs and outputs of the psoc device and their physical counterparts in t he printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the voltage is lower than a pre-set level. this is one type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and programmable system-on- chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware reset and software reset. rom an acronym for read only memory. a data-storage device from which data can be read out, but new data cannot be written in. glossary (continued) [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 42 of 44 serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register a memory storage device t hat sequentially shifts a word either left or right to output a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, th e slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. the controlling device is called the master device. sram an acronym for static random access memory. a memory device where you can store and retrieve data at a high rate of speed. the term static is used because, after a value is loaded into an sram cell, it remains unchanged until it is explicitly al tered or until power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is syn chronized by a clock signal. tri-state a function whose output ca n adopt three states: 0, 1, and z (high-impedance). the function does not drive any value in the z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowin g another output to drive the same net. uart a uart or universal asynchronous receiver-tra nsmitter translates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardw are/firmware peripheral functions that take care of managing and configuring the lower level analog and digital psoc blocks. user modules also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the re gisters in this bank are more likely to be modified during normal program execution and not just durin g initialization. registers in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of time. glossary (continued) [+] feedback
cy8cled02 document number: 001-13704 rev. *e page 43 of 44 document history page document title : cy8cled02 ez-color tm hb led controller document number: 001-13704 revision ecn # submission date origin of change description of change ** 1383443 see ecn sfvtmp3/aesa new document *a 2732564 07/09/2009 cgx converted from preliminary to final *b 2794355 10/28/2009 xbm added ?contents? on page 2 updated ?development tools? on page 6. corrected fcpu1 and fcpu2 parameters in table 21, ?5-v and 3.3-v ac chip-level specifications,? on page 21 and table 22, ?2.7-v ac chip-level specifications,? on page 22 *c 2850593 01/14/2010 fre updated dc gpio, ac chip-level, and ac programming specifications as follows: modified fimo6 and twri te specifications. replaced tramp (time) specificat ion with srpower_up (slew rate) specification. added note to flash endurance specification. added ioh, iol, dcilo, f32k_u, tpowerup, teraseall, tprogram_hot, and tprogram_cold specifications. corrected the pod kit part numbers. updated development tool selection . updated copyright and sales, solutions, and legal information urls. updated 24-pin qfn package diagram. *d 2903043 04/01/2010 njf updated cypress website links added t baketemp and t baketime parameters updated package diagrams removed sections ?third party tools? and ?build a psoc emulator? *e 3111554 12/15/10 njf added dc i 2 c specifications table. added f 32k_u max limit. added tjit_imo specification, remo ved existing jitter specifications. updated units of measure, acronyms, glossary, and references sections. updated solder reflow specifications. no specific changes were made to ac digital block specifications table and i 2 c timing diagram. they were updated for clearer understanding. [+] feedback
document number: 001-13704 rev. *e revised december 15, 2010 page 44 of 44 psoc designer? and ez-color? are trademarks and psoc? is a registered trademark of cypress semiconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cy8cled02 ? cypress semiconductor corporation, 2007-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s r epresentatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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